1. Field of the Invention
The present invention relates to bipolar transistors and particularly to vertical bipolar transistors in SOI technology as well as the production of the same.
2. Description of the Prior Art
When applying bipolar transistors in the analog domain, high demands are made on noiselessness, high-speed and high-frequency capability, respectively, and the power consumption of bipolar transistors. Additionally, for cost reduction, there is the desire to be able to produce bipolar transistors via standard methods, such as in CMOS technology (CMOS=complementary metal oxide semiconductor).
In H. Nii, etc., “A 67 GHz fmax Lateral Bipolar Transistor with Co-silicid Base Electrode Structure on Thin Film SOI for RF Analog Applications”, in Maes, H. etc., ESSDERC '99, Proceedings of the 29th European Solid-State Device Research Conference, Leuven '99, pp. 212–215, a lateral bipolar transistor in SOI technology is described. The production of the bipolar transistor starts from an SOI substrate consisting of a SOI (silicon on isolator) layer and a BOX (BOX=buried oxide) layer. First, N− collector ions are implanted in the SOI layer. Then, a polysilicon layer is deposited on the SOI layer and implanted with BF2. Apart from a small lateral area, the polycrystalline layer and the monocrystalline silicon of the SOI layer are etched into the SOI layer. A lateral NPN bipolar transistor is realized in the SOI layer by tilted B and BF2 implantation and implantations of emitter and collector ions. A Co-silicide base electrode is formed at the polysilicon layer as base terminal.
In K. Washio, “A 0.2-μm 180-GHZ-fmax 6.7-ps-ECL SOI/HRS Self-Aligned SEG SiGe HPT/CMOS Technology for Microwave and High Speed Digital Application”, IEDM 2000, pp. 741–744, a CMOS heterostructure bipolar transistor on SOI base is described, where a collector well is formed in the SOI layer and where the base, base terminal and emitter region are formed by polysilicon deposition, so that this heterostructure bipolar transistor has a double polysilicon layer structure.
In W. Klein, etc., “75 GHz Bipolar Production-Technology for the 21st Century”, in Maes, H. etc., ESSDERC '99, Proceedings of the 29th European Solid-State Device Research Conference, Leuven '99, pp. 88–94, a bipolar transistor is described, whose structure corresponds to the one shown in FIG. 3. The bipolar transistor 500 shown in FIG. 3 consists of a p substrate 502, an oxide layer 504, a polysilicon layer 506, a second oxide layer 508, an isolation layer 510 and a metal layer 518, which have been processed appropriately, to result in the bipolar transistor 500.
The bipolar transistor 500 as shown in FIG. 3 requires the following production steps for its construction. First, oxide ridges 520a, 520b and 520c are formed in the p substrate 502 by a Locos method or a trench isolation technique (STI; STI=shallow trench isolation). Then, an n collector well 522 is formed in the p substrate by high-energy implantation. The oxide layer 504 is deposited on this structure. Then, the polysilicon layer 506 is deposited on the layer 504 and subjected to a p+ doping. Subsequently, the second oxide layer 508 and a further layer (not shown in the final state in FIG. 3, since it will be removed prior to completion) are deposited on the layer 506. Then, the stack of layers 508, 506 and 504 will be structured appropriately to form a base terminal 524 of the polysilicon layer 506 and a hole 526 in the stack of layers 506, 508 and the layer of nitride. A nitride sidewall spacer, which defines an emitter window 530, is generated in the hole 526 by an appropriate method. Through the emitter window 530, a base region 532 is formed by wet etching, wherein an epitaxy base region 532 is formed by selective epitaxial growth. After a nitride removal, where the nitride layer, which is not shown, is removed, and a further generation of a spacer 528, n doped polycrystalline silicon is deposited and structured to form an emitter region 534. By depositing the isolation layer 510, providing vias 536, 538 and 540 for contacting the base terminal 524, the emitter region 534 and the n collector well 522, respectively, and by providing the metal contacts 542, 544 and 546 in the metal layer 518, the production of the bipolar transistor 500 is completed.
The disadvantage of the bipolar transistor shown in FIG. 3 is its relatively expensive production. Particularly, five layers have to be deposited on the substrate 502 for producing the bipolar transistor, namely the oxide layer 504, the polysilicon layer 506, the second oxide layer 508, the nitride layer and the polycrystalline material of the emitter terminal 534.